1. Field of the Invention
The present invention provides a frequency divider, and more particularly, a frequency divider for generating odd-number and even-number divided frequencies with a 50% duty cycle.
2. Description of the Prior Art
Digital integrated circuits have been highly developed. Personal computers, mobile phones, digital watches, and calculators, for example, are applications of digital integrated circuits. A complex digital integrated circuit often includes a plurality of divided frequencies used to enable each device in the circuit to operate properly. For example, because a CPU and a RAM operate using different clocks, a computer system should provide different divided frequencies for the CPU and the RAM to keep synchronization.
Please refer to FIG. 1, which illustrates a schematic diagram of a prior art frequency divider 10. The frequency divider 10 includes a comparator 12 and a counter 14. The comparator 12 compares a dividing number n with a count of the counter 14. When the dividing number n equals the count of the counter 14, the comparator 12 outputs a high-level square wave. The counter 14 outputs a sequence of counts according to rising edges of a reference frequency Fref, and is reset by the high-level square wave of the comparator 12, so as to output a sequence of count cycles Scn. Therefore, the frequency divider 10 can output a one-n'th frequency Fcn with a closed loop formed by the comparator 12 and the counter 14. For example, when outputting a one-second frequency Fc2, the frequency divider 10 sets the sequence of count cycles Scn of the counter 14 to be two counts for one cycle. As to operations of the frequency divider 10 when outputting one-second frequency Fc2, please refer to FIG. 2, which illustrates a waveform diagram versus time sequence. In FIG. 2, a count cycle Sc2 represents the two-count cycle provided by the counter 14. As mentioned above, the counter 14 is triggered by the rising edges of the reference frequency Fref, so when the count of the counter 14 is 2, the comparator 12 outputs a high-level signal. Meanwhile, the counter 14 is reset with the high-level square waves provided by the comparator 12 for counting from 1 again. As a result, the frequency divider 10 can output the one-second frequency Fc2 with a 50% duty cycle from the comparator 12.
However, when outputting a one-n'th frequency with an odd number n (such as 1/3, 1/5, and 1/7 frequencies), the output frequency Fcn of the prior art frequency divider 10 has asymmetric duty cycles. Please refer to FIG. 3, which illustrates a waveform diagram of the prior art frequency divider 10 when outputting a one-third frequency Fc3. As mentioned above, the counter 14 is triggered with the rising edges of the reference frequency Fref, so that when the count of the counter 14 is 3, the comparator 12 outputs a high-level signal. Meanwhile, the counter 14 is reset with the high-level square waves provided by the comparator 12 for counting from 1 again. As a result, the frequency divider 10 outputs the one-third frequency Fc3 from the comparator 12 with about a 33% duty cycle, as shown in FIG. 3.
For those systems operated in low frequency bands, as long as all devices in the systems are triggered with either rising edges of the frequency Fcn or falling edges of the frequency Fcn, the asymmetric frequency Fcn of the prior art frequency divider 10 does not affect the systems. However, in high-frequency or high-speed applications, some devices in a system are triggered with the rising edges of the frequency Fcn, and the other are triggered with the falling edges, so the asymmetry of the frequency Fcn will cause a serious problem in system synchronization. Although the frequency divider 10 can properly output 1/n frequencies having 50% duty cycles with even numbers n as shown in FIG. 2, the frequency divider 10 should output 1/n frequencies with odd numbers n to a duty-cycle recovery unit for converting the asymmetric duty cycles to be symmetric duty cycles. Therefore, when a system needs both odd-number and even-number divided frequencies, the system should include an even-number frequency divider and an odd-number frequency divider with a duty-cycle recovery unit. However, owing to circuit limitations (such as inconsistence or noise), the duty-cycle of the odd-number frequency divider cannot completely convert asymmetries to symmetries. In short, the prior art frequency divider cannot output both even-number and odd-number divided frequencies using the same circuitry.